MTL Seminar Series: "How to Meet Semiconductor Industry Patterning Requirements of Ever Smaller Microchip Designs"
Wednesday, September 20, 2017 at 12:00pm to 1:00pm
Grier Room, 34-401 50 Vassar Street, Cambridge, MA 02139
Anton de Villiers, TEL
As the semiconductor industry drives to lower dimensions and roadmaps start moving into the single digit nanometer space for production dimensions of devices, accessing relevant dimensional scales becomes an increasing challenge to the fundamentals of physics. When the industry needs to image at four times smaller than the wavelength of light, how is that done? At every turn the challenges appear impossible unless you throw away the conventional dogma of what can and should be a reasonable limitation and find a way out of the ever increasing demands for the semiconductor industry to scale. This talk will take the attendees through the key historical developments of lithography and overview some of the modern process techniques that make our cell phones and other portable electronics possible from a lithographic patterning perspective. The building blocks of patterning in the pitch-double and pitch-quad space will be discussed as well as some of the basic methods that are deployed in the industry to extend dimensions well below the 5 nm range. Methods of building circuit features with precision of atoms in such small dimensional regimes will also be discussed. How can it possible to make a complex semiconductor device with features on the order of 5000 times smaller than a human hair?