A 1-GHz Bandwidth CT Pipelined ADC with Reduced Sensitivity to Clock Jitter

Wednesday, December 13, 2023 at 12:00pm to 1:00pm

Building 34, Grier Room A (34-401A)
50 VASSAR ST, Cambridge, MA 02139

Please join us for the Fall 2023 MTL Doctoral Dissertation Seminar, with speaker Rishabh Mittal.

Analog-to-digital converters (ADCs) are essential in modern electronics. The advances in integrated circuits (IC) technology have improved the digital signal processing significantly, bringing the ADC performance limitations to the forefront. The performance of high-speed ADCs is often limited by clock jitter. In this work, we have designed a 1-GHz CT pipeline ADC with state-of-the-art performance and demonstrated improved tolerance to clock jitter.

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EECS, circuits



Microsystems Technology Laboratories
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