Wednesday, December 13, 2023 | 12pm to 1pm
About this Event
50 VASSAR ST, Cambridge, MA 02139
https://www.mtl.mit.edu/events-seminars/events/1-ghz-bandwidth-ct-pipelined-adc-reduced-sensitivity-clock-jitterPlease join us for the Fall 2023 MTL Doctoral Dissertation Seminar, with speaker Rishabh Mittal.
Analog-to-digital converters (ADCs) are essential in modern electronics. The advances in integrated circuits (IC) technology have improved the digital signal processing significantly, bringing the ADC performance limitations to the forefront. The performance of high-speed ADCs is often limited by clock jitter. In this work, we have designed a 1-GHz CT pipeline ADC with state-of-the-art performance and demonstrated improved tolerance to clock jitter.